module div(rst,clock,clk_out);
input rst,clock;
output clk_out;
reg clk_out;
reg[25:0] m;

always@(posedge clock)
begin 
	if(!rst)
		begin clk_out<=0;m<=0; end
	else
		begin 
		m<=m+1;
		if(m==12500000) clk_out<=~clk_out;
		if(m==25000000)  
		begin m<=0;
				clk_out<=~clk_out; 
			end
		end
end


endmodule  